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rev 1.1.20 1/13/03 characteristics subject to change without notice. 1 of 28 www.xicor.com 4k (512 x 8) 2-wire rtc real time clock/calendar/cpu supervisor with eeprom features real time clock/calendar tracks time in hours, minutes, and seconds day of the week, day, month, and year 2 polled alarms (non-volatile) settable on the second, minute, hour, day of the week, day, or month repeat mode (periodic interrupts) oscillator compensation on chip internal feedback resistor and compensation capacitors 64 position digitally controlled trim capacitor 6 digital frequency adjustment settings to ?0ppm cpu supervisor functions power on reset, low voltage sense watchdog timer (sw selectable: 0.25s, 0.75s, 1.75s, off) battery switch or super cap input 4k x 8 bits of eeprom 64-byte page write mode 8 modes of block lock protection single byte write capability high reliability data retention: 100 years endurance: 100,000 cycles per byte 2-wire interface interoperable with i2c* 400khz data transfer rate low power cmos 1.25? operating current (typical) small package options 8-lead soic and 8-lead tssop applications utility meters hvac equipment audio / video components set top box / television modems network routers, hubs, switches, bridges cellular infrastructure equipment fixed broadband wireless equipment pagers / pda pos equipment test meters / fixtures of?e automation (copiers, fax) home appliances computer products other industrial / medical / automotive description the x1227 device is a real time clock with clock/ calendar, two polled alarms with integrated 512x8 eeprom, oscillator compensation, cpu supervisor (por/lvs and wdt) and battery backup switch. the oscillator uses an external, low-cost 32.768khz crystal. all compensation and trim components are integrated on the chip. this eliminates several external discrete components and a trim capacitor, saving board area and component cost. x1227 block diagram x1 x2 oscillator frequency timer logic divider calendar 8 control/ registers 1hz time keeping registers alarm regs compare mask reset control decode logic alarm (eeprom) (eeprom) scl sda serial interface decoder 4k eeprom array watchdog timer low voltage reset registers status (sram) v cc v back 32.768khz (sram) battery circuitry switch osc compensation *i2c is a trademark of philips. new features repetitive alarms & temperature compensation
x1227 rev 1.1.20 1/13/03 characteristics subject to change without notice. 2 of 28 www.xicor.com description (continued) the real-time clock keeps track of time with separate registers for hours, minutes, seconds. the calendar has separate registers for date, month, year and day- of-week. the calendar is correct through 2099, with automatic leap year correction. the powerful dual alarms can be set to any clock/ calendar value for a match. for instance, every minute, every tuesday, or 5:23 am on march 21. the alarms can be polled in the status register. there is a repeat mode for the alarms allowing a periodic interrupt. the x1227 device integrates cpu supervisor func- tions and a battery switch. there is a power-on reset (reset output) with typically 250 ms delay from power on. it will also assert reset when vcc goes below the speci?d threshold. the v trip threshold is user repro- grammable. there is a watchdog timer (wdt) with 3 selectable time-out periods (0.25s, 0.75s, 1.75s) and a disabled setting. the watchdog activates the reset pin when it expires. the device offers a backup power input pin. this v back pin allows the device to be backed up by battery or supercap. the entire x1227 device is fully operational from 2.7 to 5.5 volts and the clock/calendar portion of the x1227 device remains fully operational down to 1.8 volts (standby mode). the x1227 device provides 4k bits of eeprom with 8 modes of blocklock control. the blocklock allows a safe, secure memory for critical user and con?uration data, while allowing a large user storage area. pin descriptions serial clock (scl) the scl input is used to clock all data into and out of the device. the input buffer on this pin is always active (not gated). serial data (sda) sda is a bidirectional pin used to transfer data into and out of the device. it has an open drain output and may be wire ored with other open drain or open collector outputs. the input buffer is always active (not gated). an open drain output requires the use of a pull-up resistor. the output circuitry controls the fall time of the output signal with the use of a slope controlled pull- down. the circuit is designed for 400khz 2-wire inter- face speeds. v back this input provides a backup supply voltage to the device. v back supplies power to the device in the event the v cc supply fails. this pin can be connected to a battery, a supercap or tied to ground if not used. reset output ?reset this is a reset signal output. this signal noti?s a host processor that the watchdog time period has expired or that the voltage has dropped below a ?ed v trip thresh- old. it is an open drain active low output. recom- mended value for the pullup resistor is 5k ohms. if unused, tie to ground. x1, x2 the x1 and x2 pins are the input and output, respectively, of an inverting ampli?r. an external 32.768khz quartz crystal is used with the x1227 to supply a timebase for the real time clock. the recommended crystal is a citizen cfs206-32.768kdzf. internal compensation circuitry is included to form a complete oscillator circuit. care should be taken in the placement of the crystal and the layout of the circuit. plenty of ground plane around the device and short traces to x1 and x2 are highly recommended. see application section for more recommendations. figure 1. recommended crystal connection nc = no internal connection x1227 x1 x2 v back v cc reset scl sda v ss 1 2 3 4 7 8 6 5 8-pin tssop x1227 x1 x2 v back v cc reset scl sda v ss 1 2 3 4 7 8 6 5 8-pin soic x1 x2
x1227 rev 1.1.20 1/13/03 characteristics subject to change without notice. 3 of 28 www.xicor.com power control operation the power control circuit accepts a v cc and a v back input. the power control circuit powers the device from v back when v cc < v back - 0.2v. it will switch back to power the device from v cc when v cc exceeds v back . figure 2. power control real time clock operation the real time clock (rtc) uses an external 32.768khz quartz crystal to maintain an accurate internal representation of the second, minute, hour, day, date, month, and year. the rtc has leap-year correction. the clock also corrects for months having fewer than 31 days and has a bit that controls 24 hour or am/pm format. when the x1227 powers up after the loss of both v cc and v back , the clock will not operate until at least one byte is written to the clock register. reading the real time clock the rtc is read by initiating a read command and specifying the address corresponding to the register of the real time clock. the rtc registers can then be read in a sequential read mode. since the clock runs continuously and a read takes a ?ite amount of time, there is the possibility that the clock could change during the course of a read operation. in this device, the time is latched by the read command (falling edge of the clock on the ack bit prior to rtc data output) into a separate latch to avoid time changes during the read operation. the clock continues to run. alarms occurring during a read are unaffected by the read operation. writing to the real time clock the time and date may be set by writing to the rtc registers. to avoid changing the current time by an uncompleted write operation, the current time value is loaded into a separate buffer at the falling edge of the clock on the ack bit before the rtc data input bytes, the clock continues to run. the new serial input data replaces the values in the buffer. this new rtc value is loaded back into the rtc register by a stop bit at the end of a valid write sequence. an invalid write operation aborts the time update procedure and the contents of the buffer are discarded. after a valid write operation the rtc will re?ct the newly loaded data beginning with the next ?ne second clock cycle after the stop bit is written. the rtc continues to update the time while an rtc register write is in progress and the rtc continues to run during any nonvolatile write sequences. a single byte may be written to the rtc without affecting the other bytes. accuracy of the real time clock the accuracy of the real time clock depends on the frequency of the quartz crystal that is used as the time base for the rtc. since the resonant frequency of a crystal is temperature dependent, the rtc perfor- mance will also be dependent upon temperature. the frequency deviation of the crystal is a fuction of the turnover temperature of the crystal from the crystals nominal frequency. for example, a >20ppm frequency deviation translates into an accuracy of >1 minute per month. these parameters are available from the crystal manufacturer. xicors rtc family provides on- chip crystal compensation networks to adjust load- capacitance to tune oscillator frequency from +116 ppm to ?7 ppm when using a 12.5 pf load crystal. for more detail information see the application section. clock/control registers (ccr) the control/clock registers are located in an area separate from the eeprom array and are only accessible following a slave byte of ?101111x and reads or writes to addresses [0000h:003fh]. the clock/control memory map has memory addresses from 0000h to 003fh. the de?ed addresses are described in the table 1. writing to and reading from the unde?ed addresses are not recommended. ccr access the contents of the ccr can be modi?d by perform- ing a byte or a page write operation directly to any address in the ccr. prior to writing to the ccr (except the status register), however, the wel and rwel bits must be set using a two step process (see section ?riting to the clock/control registers.) the ccr is divided into 5 sections. these are: 1. alarm 0 (8 bytes; non-volatile) 2. alarm 1 (8 bytes; non-volatile) 3. control (4 bytes; non-volatile) 4. real time clock (8 bytes; volatile) 5. status (1 byte; volatile) v back in voltage v cc on off
x1227 rev 1.1.20 1/13/03 characteristics subject to change without notice. 4 of 28 www.xicor.com table 1. clock/control memory map addr. type reg name bit range default 76543210 (optional) 003f status sr bat al1 al0 0 0 rwel wel rtcf 01h 0037 rtc (sram) y2k 0 0 y2k21 y2k20 y2k13 0 0 y2k10 19/20 20h 0036 dw 0 0 0 0 0 dy2 dy1 dy0 0-6 00h 0035 yr y23 y22 y21 y20 y13 y12 y11 y10 0-99 00h 0034 mo 0 0 0 g20 g13 g12 g11 g10 1-12 00h 0033 dt 0 0 d21 d20 d13 d12 d11 d10 1-31 00h 0032 hr mil 0 h21 h20 h13 h12 h11 h10 0-23 00h 0031 mn 0 m22 m21 m20 m13 m12 m11 m10 0-59 00h 0030 sc 0 s22 s21 s20 s13 s12 s11 s10 0-59 00h 0013 control (eeprom) dtr 0 0 0 0 0 dtr2 dtr1 dtr0 00h 0012 atr 0 0 atr5 atr4 atr3 atr2 atr1 atr0 00h 0011 int unused 0010 bl bp2 bp1 bp0 wd1 wd0 0 0 0 00h 000f alarm1 (eeprom) y2k1 0 0 a1y2k21 a1y2k20 a1y2k13 0 0 a1y2k10 19/20 20h 000e dwa1 edw1 0 0 0 0 dy2 dy1 dy0 0-6 00h 000d yra1 unused - default = rtc year value (no eeprom) - future expansion 000c moa1 emo1 0 0 a1g20 a1g13 a1g12 a1g11 a1g10 1-12 00h 000b dta1 edt1 0 a1d21 a1d20 a1d13 a1d12 a1d11 a1d10 1-31 00h 000a hra1 ehr1 0 a1h21 a1h20 a1h13 a1h12 a1h11 a1h10 0-23 00h 0009 mna1 emn1 a1m22 a1m21 a1m20 a1m13 a1m12 a1m11 a1m10 0-59 00h 0008 sca1 esc1 a1s22 a1s21 a1s20 a1s13 a1s12 a1s11 a1s10 0-59 00h 0007 alarm0 (eeprom) y2k0 0 0 a0y2k21 a0y2k20 a0y2k13 0 0 a0y2k10 19/20 20h 0006 dwa0 edw0 0 0 0 0 dy2 dy1 dy0 0-6 00h 0005 yra0 unused - default = rtc year value (no eeprom) - future expansion 0004 moa0 emo0 0 0 a0g20 a0g13 a0g12 a0g11 a0g10 1-12 00h 0003 dta0 edt0 0 a0d21 a0d20 a0d13 a0d12 a0d11 a0d10 1-31 00h 0002 hra0 ehr0 0 a0h21 a0h20 a0h13 a0h12 a0h11 a0h10 0-23 00h 0001 mna0 emn0 a0m22 a0m21 a0m20 a0m13 a0m12 a0m11 a0m10 0-59 00h 0000 sca0 esc0 a0s22 a0s21 a0s20 a0s13 a0s12 a0s11 a0s10 0-59 00h each register is read and written through buffers. the non-volatile portion (or the counter portion of the rtc) is updated only if rwel is set and only after a valid write operation and stop bit. a sequential read or page write operation provides access to the contents of only one section of the ccr per operation. access to another sec- tion requires a new operation. continued reads or writes, once reaching the end of a section, will wrap around to the start of the section. a read or write can begin at any address in the ccr. it is not necessary to set the rwel bit prior to writing the status register. section 5 supports a single byte read or write only. continued reads or writes from this section terminates the operation. the state of the ccr can be read by performing a ran- dom read at any address in the ccr at any time. this returns the contents of that register location. addi- tional registers are read by performing a sequential read. the read instruction latches all clock registers into a buffer, so an update of the clock does not change the time being read. a sequential read of the ccr will not result in the output of data from the mem- ory array. at the end of a read, the master supplies a stop condition to end the operation and free the bus. after a read of the ccr, the address remains at the previous address +1 so the user can execute a current address read of the ccr and continue reading the next register. alarm registers there are two alarm registers whose contents mimic the contents of the rtc register, but add enable bits and exclude the 24 hour time selection bit. the enable bits specify which registers to use in the comparison between the alarm and real time registers. for example: setting the enable month bit (emon*) bit in combi- nation with other enable bits and a speci? alarm time, the user can establish an alarm that triggers at the same time once a year. *n = 0 for alarm 0: n = 1 for alarm 1
x1227 rev 1.1.20 1/13/03 characteristics subject to change without notice. 5 of 28 www.xicor.com when there is a match, an alarm ?g is set. the occur- rence of an alarm can be determined by polling the al0 and al1 bits or by enabling the irq output, using it as hardware ?g. the alarm enable bits are located in the msb of the particular register. when all enable bits are set to ?? there are no alarms. the user can set the x1227 to alarm every wednes- day at 8:00 am by setting the edwn*, the ehrn* and emnn* enable bits to ? and setting the dwan*, hran* and mnan* alarm registers to 8:00 am wednesday. a daily alarm for 9:30pm results when the ehrn* and emnn* enable bits are set to ? and the hran* and mnan* registers are set to 9:30 pm. *n = 0 for alarm 0: n = 1 for alarm 1 real time clock registers clock/calendar registers (sc, mn, hr, dt, mo, yr) these registers depict bcd representations of the time. as such, sc (seconds) and mn (minutes) range from 00 to 59, hr (hour) is 1 to 12 with an am or pm indicator (h21 bit) or 0 to 23 (with mil=1), dt (date) is 1 to 31, mo (month) is 1 to 12, yr (year) is 0 to 99. date of the week register (dw) this register provides a day of the week status and uses three bits dy2 to dy0 to represent the seven days of the week. the counter advances in the cycle 0-1-2-3-4-5-6-0-1-2-?the assignment of a numerical value to a speci? day of the week is arbitrary and may be decided by the system software designer. the default value is de?ed as ?? 24 hour time if the mil bit of the hr register is 1, the rtc uses a 24-hour format. if the mil bit is 0, the rtc uses a 12- hour format and h21 bit functions as an am/pm indi- cator with a ? representing pm. the clock defaults to standard time with h21=0. leap years leap years add the day february 29 and are de?ed as those years that are divisible by 4. years divisible by 100 are not leap years, unless they are also divisible by 400. this means that the year 2000 is a leap year, the year 2100 is not. the x1227 does not correct for the leap year in the year 2100. status register (sr) the status register is located in the ccr memory map at address 003fh. this is a volatile register only and is used to control the wel and rwel write enable latches, read two power status and two alarm bits. this register is separate from both the array and the clock/control registers (ccr). table 2. status register (sr) bat: battery supply?olatile this bit set to ? indicates that the device is operating from v back , not v cc . it is a read-only bit and is set/ reset by hardware (x1227 internally). once the device begins operating from v cc , the device sets this bit to ?? al1, al0: alarm bits?olatile these bits announce if either alarm 0 or alarm 1 match the real time clock. if there is a match, the respective bit is set to ?? the falling edge of the last data bit in a sr read operation resets the ?gs. note: only the al bits that are set when an sr read starts will be reset. an alarm bit that is set by an alarm occurring during an sr read operation will remain set after the read opera- tion is complete. rwel: register write enable latch?olatile this bit is a volatile latch that powers up in the low (disabled) state. the rwel bit must be set to ? prior to any writes to the clock/control registers. writes to rwel bit do not cause a nonvolatile write cycle, so the device is ready for the next operation immediately after the stop condition. a write to the ccr requires both the rwel and wel bits to be set in a speci? sequence. wel: write enable latch?olatile the wel bit controls the access to the ccr and memory array during a write operation. this bit is a volatile latch that powers up in the low (disabled) state. while the wel bit is low, writes to the ccr or any array address will be ignored (no acknowledge will be issued after the data byte). the wel bit is set by writing a ? to the wel bit and zeroes to the other bits of the status register. once set, wel remains set until either reset to 0 (by writing a ? to the wel bit and zeroes to the other bits of the status register) or addr 7 6 5 4 3 2 1 0 003fh bat al1 al0 0 0 rwel wel rtcf default 0 0 0 0 0 0 0 1
x1227 rev 1.1.20 1/13/03 characteristics subject to change without notice. 6 of 28 www.xicor.com until the part powers up again. writes to wel bit do not cause a nonvolatile write cycle, so the device is ready for the next operation immediately after the stop condition. rtcf: real time clock fail bit?olatile this bit is set to a ? after a total power failure. this is a read only bit that is set by hardware (x1227 inter- nally) when the device powers up after having lost all power to the device. the bit is set regardless of whether v cc or v back is applied ?st. the loss of only one of the supplies does not result in setting the rtcf bit. the ?st valid write to the rtc after a complete power failure (writing one byte is suf?ient) resets the rtcf bit to ?? unused bits: this device does not use bits 3 or 4 in the sr, but must have a zero in these bit positions. the data byte output during a sr read will contain zeros in these bit locations. control registers the control bits and registers, described under this section, are nonvolatile. block protect bits?p2, bp1, bp0 the block protect bits, bp2, bp1 and bp0, determine which blocks of the array are write protected. a write to a protected block of memory is ignored. the block protect bits will prevent write operations to one of eight segments of the array. the partitions are described in table 3 . table 3. block protect bits watchdog timer control bits?d1, wd0 the bits wd1 and wd0 control the period of the watchdog timer. see table 4 for options. table 4. watchdog timer time-out options on-chip oscillator compensation digital trimming register (dtr) ?dtr2, dtr1 and dtr0 (non-volatile) the digital trimming bits dtr2, dtr1 and dtr0 adjust the number of counts per second and average the ppm error to achieve better accuracy. dtr2 is a sign bit. dtr2=0 means frequency compensation is > 0. dtr2=1 means frequency compensation is < 0. dtr1 and dtr0 are scale bits. dtr1 gives 10 ppm adjustment and dtr0 gives 20 ppm adjustment. a range from -30ppm to +30ppm can be represented by using three bits above. table 5. digital trimming registers bp2 bp1 bp0 protected addresses x1227 array lock 0 0 0 none (default) none 001 180 h ?1ff h upper 1/4 010 100 h ?1ff h upper 1/2 011 000 h ?1ff h full array 100 000 h ?03f h first page 101 000 h ?07f h first 2 pgs 110 000 h ?0ff h first 4 pgs 111 000 h ?1ff h first 8 pgs wd1 wd0 watchdog time-out period 0 0 1.75 seconds (factory default) 0 1 750 milliseconds 1 0 250 milliseconds 1 1 disabled dtr register estimated frequency ppm dtr2 dtr1 dtr0 0 0 0 0 (default) 0 1 0 +10 0 0 1 +20 0 1 1 +30 100 0 1 1 0 -10 1 0 1 -20 1 1 1 -30
x1227 rev 1.1.20 1/13/03 characteristics subject to change without notice. 7 of 28 www.xicor.com analog trimming register (atr) (non-volatile) six analog trimming bits from atr5 to atr0 are pro- vided to adjust the on-chip loading capacitance range. the on-chip load capacitance ranges from 3.25pf to 18.75pf. each bit has a different weight for capaci- tance adjustment. using a citizen cfs-206 crystal with different atr bit combinations provides an esti- mated ppm range from +116ppm to -37ppm to the nominal frequency compensation. the combination of digital and analog trimming can give up to +146ppm adjustment. the on-chip capacitance can be calculated as follows: c at r = [(atr value, decimal) x 0.25pf] + 11.0pf note that the atr values are in twos complement, with atr(000000) = 11.0pf, so the entire range runs from 3.25pf to 18.75pf in 0.25pf steps. the values calculated above are typical, and total load capacitance seen by the crystal will include approxi- mately 2pf of package and board capacitance in addi- tion to the atr value. see application section and xicors application note an154 for more information. writing to the clock/control registers changing any of the nonvolatile bits of the clock/con- trol register requires the following steps: write a 02h to the status register to set the write enable latch (wel). this is a volatile operation, so there is no delay after the write. (operation preceeded by a start and ended with a stop). write a 06h to the status register to set both the register write enable latch (rwel) and the wel bit. this is also a volatile cycle. the zeros in the data byte are required. (operation preceeded by a start and ended with a stop). write one to 8 bytes to the clock/control registers with the desired clock, alarm, or control data. this sequence starts with a start bit, requires a slave byte of ?1011110 and an address within the ccr and is terminated by a stop bit. a write to the ccr changes eeprom values so these initiate a nonvolatile write cycle and will take up to 10ms to complete. writes to unde?ed areas have no effect. the rwel bit is reset by the completion of a nonvolatile write cycle, so the sequence must be repeated to again initiate another change to the ccr contents. if the sequence is not completed for any reason (by send- ing an incorrect number of bits or sending a start instead of a stop, for example) the rwel bit is not reset and the device remains in an active mode. writing all zeros to the status register resets both the wel and rwel bits. a read operation occurring between any of the previous operations will not interrupt the register write operation.
x1227 rev 1.1.20 1/13/03 characteristics subject to change without notice. 8 of 28 www.xicor.com power on reset application of power to the x1227 activates a power on reset circuit that pulls the reset pin active. this signal provides several bene?s. it prevents the system microprocessor from starting to operate with insuf?ient voltage. it prevents the processor from operating prior to sta- bilization of the oscillator. it allows time for an fpga to download its con?ura- tion prior to initialization of the circuit. it prevents communication to the eeprom, greatly reducing the likelihood of data corruption on power up. when v cc exceeds the device v trip threshold value for typically 250ms the circuit releases reset , allow- ing the system to begin operation. recommended slew rate is between 0.2v/ms and 50v/ms. watchdog timer operation the watchdog timer is selectable. by writing a value to wd1 and wd0, the watchdog timer can be set to 3 dif- ferent time out periods or off. when the watchdog timer is set to off, the watchdog circuit is con?ured for low power operation. watchdog timer restart the watchdog timer is started by a falling edge of sda when the scl line is high and followed by a stop bit. the start signal restarts the watchdog timer counter, resetting the period of the counter back to the maximum. if another start fails to be detected prior to the watchdog timer expiration, then the reset pin becomes active. in the event that the start signal occurs during a reset time out period, the start will have no effect. when using a single start to refresh watchdog timer, a stop bit should be followed to reset the device back to stand-by mode. low voltage reset operation when a power failure occurs, and the voltage to the part drops below a ?ed v trip voltage, a reset pulse is issued to the host microcontroller. the circuitry moni- tors the v cc line with a voltage comparator which senses a preset threshold voltage. power up and power down waveforms are shown in figure 4. the low voltage reset circuit is to be designed so the reset signal is valid down to 1.0v. when the low voltage reset signal is active, the operation of any in progress nonvolatile write cycle is unaffected, allowing a nonvolatile write to continue as long as possi- ble (down to the power on reset voltage). the low voltage reset signal, when active, terminates in progress commu- nications to the device and prevents new commands, to reduce the likelihood of data corruption. figure 3. watchdog restart/time out t rsp t wdo t rsp >t wdo start stop start
x1227 rev 1.1.20 1/13/03 characteristics subject to change without notice. 9 of 28 www.xicor.com figure 4. power on reset and low voltage reset v cc v trip reset t purst t purst t r t f t rpd v rvalid v cc threshold reset procedure [optional] the x1227 is shipped with a standard v cc threshold (v trip ) voltage. this value will not change over normal operating and storage conditions. however, in applica- tions where the standard v trip is not exactly right, or if higher precision is needed in the v trip value, the x1227 threshold may be adjusted. the procedure is described below, and uses the application of a nonvol- atile write control signal. setting the v trip voltage it is necessary to reset the trip point before setting the new value. to set the new v trip voltage, apply the desired v trip threshold voltage to the v cc pin and tie the reset pin to the programming voltage v p . then write data 00h to address 01h. the stop bit following a valid write opera- tion initiates the v trip programming sequence. bring reset to v cc to complete the operation. note: this operation may take up to 10 milliseconds to complete and also writes 00h to address 01h of the eeprom array. figure 5. set v trip level sequence (v cc = desired v trip value) scl sda 01h reset v p = 15v 00h 01234567 01234567 01234567 01234567 aeh 00h v cc v cc note: bp0, bp1, bp2 must be disabled. resetting the v trip voltage this procedure is used to set the v trip to a ?ative voltage level. for example, if the current v trip is 4.4v and the new v trip must be 4.0v, then the v trip must be reset. when v trip is reset, the new v trip is some- thing less than 1.7v. this procedure must be used to set the voltage to a lower value. to reset the new v trip voltage, apply more than 5.5v to the v cc pin and tie the reset pin to the programming voltage v p . then write 00h to address 03h. the stop bit of a valid write operation initiates the v trip programming sequence. bring reset to v cc to complete the operation. note: this operation takes up to 10 milliseconds to complete and also writes 00h to address 03h of the eeprom array. for best accuracy in setting v trip , it is advised that the following sequence be used. 1.program v trip as above. 2.measure resulting v trip by measuring the v cc value where a reset occurs. calculate delta = (desired ?measured) v trip value. 3.perform a v trip program using the following formula to set the voltage of the reset pin: v reset = (desired value ?delta) + 0.025v
x1227 rev 1.1.20 1/13/03 characteristics subject to change without notice. 10 of 28 www.xicor.com serial communication interface conventions the device supports a bidirectional bus oriented proto- col. the protocol de?es any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. the device controlling the transfer is called the master and the device being controlled is called the slave. the master always initiates data trans- fers, and provides the clock for both transmit and receive operations. therefore, the devices in this family operate as slaves in all applications. clock and data data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions. see figure 7. start condition all commands are preceded by the start condition, which is a high to low transition of sda when scl is high. the device continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. see figure 8. stop condition all communications must be terminated by a stop condition, which is a low to high transition of sda when scl is high. the stop condition is also used to place the device into the standby power mode after a read sequence. a stop condition can only be issued after the transmitting device has released the bus. see figure 8. acknowledge acknowledge is a software convention used to indicate successful data transfer. the transmitting device, either master or slave, will release the bus after transmitting eight bits. during the ninth clock cycle, the receiver will pull the sda line low to acknowledge that it received the eight bits of data. refer to figure 9. the device will respond with an acknowledge after rec- ognition of a start condition and if the correct device identi?r and select bits are contained in the slave address byte. if a write operation is selected, the device will respond with an acknowledge after the receipt of each subsequent eight bit word. the device will acknowledge all incoming data and address bytes, except for: the slave address byte when the device identi?r and/or select bits are incorrect all data bytes of a write when the wel in the write protect register is low the 2nd data byte of a status register write opera- tion (only 1 data byte is allowed) in the read mode, the device will transmit eight bits of data, release the sda line, then monitor the line for an acknowledge. if an acknowledge is detected and no stop condition is generated by the master, the device will continue to transmit data. the device will terminate further data transmissions if an acknowledge is not detected. the master must then issue a stop condition to return the device to standby mode and place the device into a known state. figure 6. reset v trip level sequence 01234567 scl sda aeh 01234567 03h reset v p = 15v 00h 01234567 01234567 00h v cc v cc note: bp0, bp1, bp2 must be disabled.
x1227 rev 1.1.20 1/13/03 characteristics subject to change without notice. 11 of 28 www.xicor.com figure 7. valid data changes on the sda bus figure 8. valid start and stop conditions scl sda data stable data change data stable scl sda start stop figure 9. acknowledge response from receiver scl from master data output from transmitter data output from receiver 8 1 9 start acknowledge device addressing following a start condition, the master must output a slave address byte. the ?st four bits of the slave address byte specify access to either the eeprom array or to the ccr. slave bits ?010 access the eeprom array. slave bits ?101 access the ccr. when shipped from the factory, eeprom array is undefined, and should be programmed by the cus- tomer to a known state. bit 3 through bit 1 of the slave byte specify the device select bits. these are set to ?11? the last bit of the slave address byte de?es the oper- ation to be performed. when this r/w bit is a one, then a read operation is selected. a zero selects a write operation. refer to figure 10. after loading the entire slave address byte from the sda bus, the x1227 compares the device identi?r and device select bits with ?010111 or ?101111? upon a correct compare, the device outputs an acknowledge on the sda line. following the slave byte is a two byte word address. the word address is either supplied by the master device or obtained from an internal counter. on power up the internal address counter is set to address 0h, so a current address read of the eeprom array starts at address 0. when required, as part of a random read, the master must supply the 2 word address bytes as shown in figure 10. in a random read operation, the slave byte in the ?ummy write portion must match the slave byte in the ?ead section. that is if the random read is from the array the slave byte must be 1010111x in both instances. similarly, for a random read of the clock/ control registers, the slave byte must be 1101111x in both places.
x1227 rev 1.1.20 1/13/03 characteristics subject to change without notice. 12 of 28 www.xicor.com write operations byte write for a write operation, the device requires the slave address byte and the word address bytes. this gives the master access to any one of the words in the array or ccr. (note: prior to writing to the ccr, the master must write a 02h, then 06h to the status register in two preceding operations to enable the write operation. see ?riting to the clock/control registers. upon receipt of each address byte, the x1227 responds with an acknowledge. after receiving both address bytes the x1227 awaits the eight bits of data. after receiving the 8 data bits, the x1227 again responds with an acknowledge. the master then terminates the transfer by generating a stop condition. the x1227 then begins an internal write cycle of the data to the nonvolatile memory. during the internal write cycle, the device inputs are disabled, so the device will not respond to any requests from the master. the sda output is at high impedance. see figure 11. figure 11. byte write sequence figure 12. writing 30 bytes to a 64 -byte memory page starting at address 40 . s t a r t s t o p slave address word address 1 data a c k a c k a c k sda bus signals from the slave signals from the master 0 a c k word address 0 1 1 1 1 0000000 address address 40 23 bytes 63 7 bytes address = 6 address pointer ends here addr = 7 figure 10. slave address, word address, and data bytes (64 byte pages) slave address byte byte 0 d7 d6 d5 d2 d4 d3 d1 d0 a0 a7 a2 a4 a3 a1 data byte byte 3 a6 a5 00 000a8 0 1 1 0 1 1 0 1 0 1 1 r/w 1 device identifier array ccr 0 word address 1 byte 1 word address 0 byte 2
x1227 rev 1.1.20 1/13/03 characteristics subject to change without notice. 13 of 28 www.xicor.com a write to a protected block of memory is ignored, but will still receive an acknowledge. at the end of the write command, the x1227 will not initiate an internal write cycle, and will continue to ack commands. page write the x1227 has a page write operation. it is initiated in the same manner as the byte write operation; but instead of terminating the write cycle after the ?st data byte is transferred, the master can transmit up to 63 more bytes to the memory array and up to 7 more bytes to the clock/control registers. (note: prior to writ- ing to the ccr, the master must write a 02h, then 06h to the status register in two preceding operations to enable the write operation. see ?riting to the clock/ control registers. after the receipt of each byte, the x1227 responds with an acknowledge, and the address is internally incre- mented by one. when the counter reaches the end of the page, it ?olls over and goes back to the ?st address on the same page. this means that the mas- ter can write 64 bytes to a memory array page or 8 bytes to a ccr section starting at any location on that page. for example, if the master begins writing at loca- tion 40 of the memory and loads 30 bytes, then the ?st 23 bytes are written to addresses 45 through 63, and the last 7 bytes are written to columns 0 through 6. afterwards, the address counter would point to location 7 on the page that was just written. if the master sup- plies more than the maximum bytes in a page, then the previously loaded data is over written by the new data, one byte at a time. refer to figure 12. the master terminates the data byte loading by issu- ing a stop condition, which causes the x1227 to begin the nonvolatile write cycle. as with the byte write oper- ation, all inputs are disabled until completion of the internal write cycle. refer to figure 13 for the address, acknowledge, and data transfer sequence. stops and write modes stop conditions that terminate write operations must be sent by the master after sending at least 1 full data byte and its associated ack signal. if a stop is issued in the middle of a data byte, or before 1 full data byte + ack is sent, then the x1227 resets itself without per- forming the write. the contents of the array are not affected. figure 13. page write sequence word address 0 s t a r t s t o p slave address word address 1 data (n) a c k a c k a c k sda bus signals from the slave signals from the master 0 data (1) a c k 1 n 64 for eeprom array 1 n 8 for ccr 1 1 1 1 0000000
x1227 rev 1.1.20 1/13/03 characteristics subject to change without notice. 14 of 28 www.xicor.com acknowledge polling disabling of the inputs during nonvolatile write cycles can be used to take advantage of the typical 5ms write cycle time. once the stop condition is issued to indi- cate the end of the masters byte load operation, the x1227 initiates the internal nonvolatile write cycle. acknowledge polling can begin immediately. to do this, the master issues a start condition followed by the memory array slave address byte for a write or read operation (aeh or afh). if the x1227 is still busy with the nonvolatile write cycle then no ack will be returned. when the x1227 has completed the write operation, an ack is returned and the host can pro- ceed with the read or write operation. refer to the ?w chart in figure 15. note: do not use the ccr slave byte (deh or dfh) for acknowledge polling. read operations there are three basic read operations: current address read, random read, and sequential read. current address read internally the x1227 contains an address counter that maintains the address of the last word read incre- mented by one. therefore, if the last read was to address n, the next read operation would access data from address n+1. on power up, the sixteen bit address is initialized to 0h. in this way, a current address read immediately after the power on reset can download the entire contents of memory starting at the ?st location.upon receipt of the slave address byte with the r/w bit set to one, the x1227 issues an acknowledge, then transmits eight data bits. the mas- ter terminates the read operation by not responding with an acknowledge during the ninth clock and issuing a stop condition. refer to figure 14 for the address, acknowledge, and data transfer sequence. figure 15. acknowledge polling sequence it should be noted that the ninth clock cycle of the read operation is not a ?on? care. to terminate a read operation, the master must either issue a stop condi- tion during the ninth cycle or hold sda high during the ninth clock cycle and then issue a stop condition. ack returned? issue memory array slave address byte afh (read) or aeh (write) byte load completed by issuing stop. enter ack polling issue stop issue start no yes issue stop no continue normal read or write command sequence proceed yes nonvolatile write cycle complete. continue command sequence? figure 14. current address read sequence s t a r t s t o p slave address data a c k sda bus signals from the slave signals from the master 1 1 1 1 1
x1227 rev 1.1.20 1/13/03 characteristics subject to change without notice. 15 of 28 www.xicor.com random read random read operations allows the master to access any location in the x1227. prior to issuing the slave address byte with the r/w bit set to zero, the master must ?st perform a ?ummy write operation. the master issues the start condition and the slave address byte, receives an acknowledge, then issues the word address bytes. after acknowledging receipt of each word address byte, the master immediately issues another start condition and the slave address byte with the r/w bit set to one. this is followed by an acknowledge from the device and then by the eight bit data word. the master terminates the read operation by not responding with an acknowledge and then issu- ing a stop condition. refer to figure 16 for the address, acknowledge, and data transfer sequence. in a similar operation called ?et current address, the device sets the address if a stop is issued instead of the second start shown in figure 16. the x1227 then goes into standby mode after the stop and all bus activity will be ignored until a start is detected. this operation loads the new address into the address counter. the next current address read operation will read from the newly loaded address. this operation could be useful if the master knows the next address it needs to read, but is not ready for the data. sequential read sequential reads can be initiated as either a current address read or random address read. the ?st data byte is transmitted as with the other modes; however, the master now responds with an acknowledge, indi- cating it requires additional data. the device continues to output data for each acknowledge received. the mas- ter terminates the read operation by not responding with an acknowledge and then issuing a stop condition. the data output is sequential, with the data from address n followed by the data from address n + 1. the address counter for read operations increments through all page and column addresses, allowing the entire memory contents to be serially read during one operation. at the end of the address space the counter ?olls over to the start of the address space and the x1227 continues to output data for each acknowledge received. refer to figure 17 for the acknowledge and data transfer sequence. figure 16. random address read sequence 0 slave address word address 1 a c k a c k s t a r t s t o p slave address data a c k 1 s t a r t sda bus signals from the slave signals from the master a c k word address 0 1 1 1 1 1 1 11 0000000 figure 17. sequential read sequence data (2) s t o p slave address data (n) a c k a c k sda bus signals from the slave signals from the master 1 data (n-1) a c k a c k (n is any integer greater than 1) data (1)
x1227 rev 1.1.20 1/13/03 characteristics subject to change without notice. 16 of 28 www.xicor.com absolute maximum ratings temperature under bias ................... -65? to +135? storage temperature......................... -65? to +150? voltage on v cc , v back pin (respect to ground)...............................-0.5v to 7.0v voltage on scl, sda, x1 and x2 pin (respect to ground) ............... -0.5v to 7.0v or 0.5v above v cc or v back (whichever is higher) dc output current .............................................. 5 ma lead temperature (soldering, 10 sec) ...............300? stresses above those listed under ?bsolute maximum ratings may cause permanent damage to the device. this is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not implied. exposure to absolute max- imum rating conditions for extended periods may affect device reliability. dc operating characteristics (temperature = -40? to +85?, unless otherwise stated.) operating characteristics symbol parameter conditions min typ max unit notes v cc main power supply 2.7 5.5 v v back backup power supply 1.8 5.5 v v cb switch to backup supply v back -0.2 v back -0.1 v v bc switch to main supply v back v back +0.2 v symbol parameter conditions min typ max unit notes i cc1 read active supply current v cc = 2.7v 400 ? 1, 5, 7, 14 v cc = 5.0v 800 ? i cc2 program supply current (nonvolatile) v cc = 2.7v 2.5 ma 2, 5, 7, 14 v cc = 5.0v 3.0 ma i cc3 main timekeeping current v cc = 2.7v 10 ? 3, 7, 8, 14, 15 v cc = 5.0v 20 ? i back timekeeping current (low voltage sense and watchdog timer disabled v back = 1.8v 1.25 ? 3, 6, 9, 14, 15 ?ee perfor- mance data v back = 3.3v 1.5 ? i li input leakage current 10 ? 10 i lo output leakage current 10 a 10 v il input low voltage -0.5 v cc x 0.2 or v back x 0.2 v13 v ih input high voltage v cc x 0.7 or v back x 0.7 v cc + 0.5 or v back + 0.5 v13 v hys schmitt trigger input hysteresis v cc related level .05 x v cc or .05 x v back v13 v ol1 output low voltage for sda and reset v cc = 2.7v 0.4 v11 v cc = 5.5v 0.4
x1227 rev 1.1.20 1/13/03 characteristics subject to change without notice. 17 of 28 www.xicor.com notes: (1) the device enters the active state after any start, and remains active: for 9 clock cycles if the device select bits in the slave address byte are incorrect or until 200ns after a stop ending a read or write operation. (2) the device enters the program state 200ns after a stop ending a write operation and continues for t wc . (3) the device goes into the timekeeping state 200ns after any stop, except those that initiate a nonvolatile write cycle; t wc after a stop that initiates a nonvolatile write cycle; or 9 clock cycles after any start that is not followed by the correct device sel ect bits in the slave address byte. (4) for reference only and not tested. (5) v il = v cc x 0.1, v ih = v cc x 0.9, f scl = 400khz (6) v cc = 0v (7) v back = 0v (8) v sda = v scl =v cc , others = gnd or v cc (9) v sda =v scl =v back , others = gnd or v back (10) v sda = gnd or v cc , v scl = gnd or v cc , v reset = gnd or v cc (11) i ol = 3.0ma at 5.5v, 1.5ma at 2.7v (12) i oh = -1.0ma at 5.5v, -0.4ma at 2.7v (13) threshold voltages based on the higher of vcc or vback. (14) using recommended crystal and oscillator network applied to x1 and x2 (25?). (15) typical values are for t a = 25? capacitance t a = 25?, f = 1.0 mhz, v cc = 5v notes: (1) this parameter is not 100% tested. (2) the input capacitance between x1 and x2 pins can be varied between 5pf and 19.75pf by using analog trimming registers ac characteristics ac test conditions figure 18. standard output load for testing the device with v cc = 5.0v symbol parameter max. units test conditions c out (1) output capacitance (sda, reset )10pfv out = 0v c in (1) input capacitance (scl) 10 pf v in = 0v input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing levels v cc x 0.5 output load standard output load sda 1533 ? 100pf 5.0v for v ol = 0.4v and i ol = 3 ma equivalent ac output load circuit for v cc = 5v
x1227 rev 1.1.20 1/13/03 characteristics subject to change without notice. 18 of 28 www.xicor.com ac specifications (t a = -40? to +85?, vcc = +2.7v to +5.5v, unless otherwise specified.) notes: (1) this parameter is not 100% tested. (2) cb = total capacitance of one bus line in pf. timing diagrams bus timing symbol parameter min. max. units f scl scl clock frequency 400 khz t in pulse width suppression time at inputs 50 (1) ns t aa scl low to sda data out valid 0.1 0.9 s t buf time the bus must be free before a new transmission can start 1.3 s t low clock low time 1.3 s t high clock high time 0.6 s t su:sta start condition setup time 0.6 s t hd:sta start condition hold time 0.6 s t su:dat data in setup time 100 ns t hd:dat data in hold time 0 s t su:sto stop condition setup time 0.6 s t dh data output hold time 50 ns t r sda and scl rise time 20 +.1cb (2) 300 ns t f sda and scl fall time 20 +.1cb (2) 300 ns cb capacitive load for each bus line 400 pf t su:sto t dh t high t su:sta t hd:sta t hd:dat t su:dat scl sda in sda out t f t low t buf t aa t r
x1227 rev 1.1.20 1/13/03 characteristics subject to change without notice. 19 of 28 www.xicor.com write cycle timing power up timing notes: (1) delays are measured from the time v cc is stable until the speci?d operation can be initiated. these parameters are not 100% tested. v cc slew rate should be between 0.2mv/?ec and 50mv/?ec. (2) typical values are for t a = 25? and v cc = 5.0v nonvolatile write cycle timing note: (1) t wc is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. it is the minimum cycle time to be allowed for any nonvolatile write by the user, unless acknowledge polling is used. watchdog timer/low voltage reset operating characteristics watchdog/low voltage reset parameters (see figures 3 and 4) symbol parameter min. typ. (2) max. units t pur (1) time from power up to read 1 ms t puw (1) time from power up to write 5 ms symbol parameter min. typ. (1) max. units t wc (1) write cycle time 5 10 ms symbols parameters min. typ. max. unit v ptrip programmed reset trip voltage x1227-4.5a x1227 x1227-2.7a x1227-2.7 4.50 4.25 2.75 2.55 4.63 4.38 2.85 2.65 4.75 4.50 2.95 2.75 v t rpd v cc detect to reset low 500 ns t purst power up reset time-out delay 100 250 400 ms t f v cc fall time 10 ? t r v cc rise time 10 ? t wdo watchdog timer period (crystal=32.768khz): wd1=0, wd0=0 wd1=0, wd0=1 wd1=1, wd0=0 1.7 725 225 1.75 750 250 1.8 775 275 s ms ms t rst watchdog reset time-out delay (crystal=32.768khz) 225 250 275 ms t rsp 2-wire interface 1 s v rvalid reset valid v cc 1.0 v scl sda t wc 8th bit of last byte ack stop condition start condition
x1227 rev 1.1.20 1/13/03 characteristics subject to change without notice. 20 of 28 www.xicor.com v trip programming timing diagram v trip programming parameters parameter description min. max. units t vps v trip program enable voltage setup time 1 s t vph v trip program enable voltage hold time 1 s t tsu v trip setup time 1 s t thd v trip hold (stable) time 10 ms t vpo v trip program enable voltage off time (between successive adjustments) 0s t rp v trip program recovery period (between successive adjustments) 10 ms v p programming voltage 14 16 v v tran v trip programmed voltage range 1.7 5.0 v v tv v trip program variation after programming (programmed at 25?) -25 +25 mv v trip programming parameters are not 100% tested. 01234567 01234567 01234567 01234567 v cc (v trip ) t vph t vps t vpo t rp scl sda aeh 03h/01h reset v p = 15v 00h 00h v cc v cc t tsu t thd v trip
x1227 rev 1.1.20 1/13/03 characteristics subject to change without notice. 21 of 28 www.xicor.com application section crystal oscillator and temperature compensation xicor has now integrated the oscillator compensation circuity on-chip, to eliminate the need for external com- ponents and adjust for crystal drift over temperature and enable very high accuracy time keeping (<5ppm drift. the xicor rtc family uses an oscillator circuit with on- chip crystal compensation network, including adjust- able load-capacitance. the only external component required is the crystal. the compensation network is optimized for operation with certain crystal parameters which are common in many of the surface mount or tuning-fork crystals available today. table 6 summa- rizes these parameters. table 7 contains some crystal manufacturers and part numbers that meet the requirements for the xicor rtc products. the turnover temperature in table 6 describes the temperature where the apex of the of the drift vs. tem- perature curve occurs. this curve is parabolic with the drift increasing as (t-t0) 2 . for an epson mc-405 device, for example, the turnover temperature is typi- cally 25 deg c, and a peak drift of >110ppm occurs at the temperature extremes of ?0 and +85 deg c. it is possible to address this variable drift by adjusting the load capacitance of the crystal, which will result in pre- dictable change to the crystal frequency. the xicor rtc family allows this adjustment over temperature since the devices include on-chip load capacitor trim- ming. this control is handled by the analog trimming register, or atr, which has 6 bits of control. the load capacitance range covered by the atr circuit is approximately 3.25pf to 18.75pf, in 0.25pf incre- ments. note that actual capacitance would also include about 2pf of package related capacitance. in- circuit tests with commercially available crystals dem- onstrate that this range of capacitance allows fre- quency control from +116ppm to ?7ppm, using a 12.5pf load crystal. in addition to the analog compensation afforded by the adjustable load capacitance, a digital compensation feature is available for the xicor rtc family. there are three bits known as the digital trimming register or dtr, and they operate by adding or skipping pulses in the clock signal. the range provided is ?0ppm in increments of 10ppm. the default setting is 0ppm. the dtr control can be used for coarse adjustments of frequency drift over temperature or for crystal initial accuracy correction. table 6. crystal parameters required for xicor rtc? table 7. crystal manufacturers parameter min typ max units notes frequency 32.768 khz freq. tolerance ?00 ppm down to 20ppm if desired turnover temperature 20 25 30 ? typically the value used for most crystals operating temperature range -40 85 ? parallel load capacitance 12.5 pf equivalent series resistance 50 k ? for best oscillator performance manufacturer part number temp range +25? freq toler. citizen cm201, cm202, cm200s -40 to +85? ?0ppm epson mc-405, mc-406 -40 to +85? ?0ppm raltron rsm-200s-a or b -40 to +85? ?0ppm saronix 32s12a or b -40 to +85? ?0ppm ecliptek ecpsm29t-32.768k -10 to +60? ?0ppm ecs ecx-306/ecx-306i -10 to +60? ?0ppm fox fsm-327 -40 to +85? ?0ppm
x1227 rev 1.1.20 1/13/03 characteristics subject to change without notice. 22 of 28 www.xicor.com a ?al application for the atr control is in-circuit cali- bration for high accuracy applications, along with a temperature sensor chip. once the rtc circuit is pow- ered up with battery backup, the frequency drift is mea- sured. the atr control is then adjusted to a setting which minimizes drift. once adjusted at a particular temperature, it is possible to adjust at other discrete temperatures for minimal overall drift, and store the resulting settings in the eeprom. extremely low over- all temperature drift is possible with this method. the xicor evaluation board contains the circuitry necessary to implement this control. for more detailed operation see xicors application note an154 on xicors website at www.xicor.com. layout considerations the crystal input at x1 has a very high impedance and will pick up high frequency signals from other circuits on the board. since the x2 pin is tied to the other side of the crystal, it is also a sensitive node. these signals can couple into the oscillator circuit and produce dou- ble clocking or mis-clocking, seriously affecting the accuracy of the rtc. care needs to be taken in layout of the rtc circuit to avoid noise pickup. below in fig- ure 15 is a suggested layout for the x1226 or x1227 devices. figure 15. suggested layout for xicor rtc in so-8 the x1 and x2 connections to the crystal are to be kept as short as possible. a thick ground trace around the crystal is advised to minimize noise intrusion, but ground near the x1 and x2 pins should be avoided as it will add to the load capacitance at those pins. keep in mind these guidelines for other pcb layers in the vicin- ity of the rtc device. a small decoupling capacitor at the vcc pin of the chip is mandatory, with a solid con- nection to ground. for other rtc products, the same rules stated above should be observed, but adjusted slightly since the packages and pinouts are slightly different. assembly most electronic circuits do not have to deal with assembly issues, but with the rtc devices assembly includes insertion or soldering of a live battery into an unpowered circuit. if a socket is soldered to the board, and a battery is inserted in ?al assembly, then there are no issues with operation of the rtc. if the battery is soldered to the board directly, then the rtc device vback pin will see some transient upset from either sol- dering tools or intermittent battery connections which can stop the circuit from oscillating. once the battery is soldered to the board, the only way to assure the circuit will start up is to momentarily (very short period of time!) short the vback pin to ground and the circuit will begin to oscillate. oscillator measurements when a proper crystal is selected and the layout guide- lines above are observed, the oscillator should start up in most circuits in less than one second. some circuits may take slightly longer, but startup should de?itely occur in less than 5 seconds. when testing rtc cir- cuits, the most common impulse is to apply a scope probe to the circuit at the x2 pin (oscillator output) and observe the waveform. do not do this! although in some cases you may see a useable waveform, due to the parasitics (usually 10pf to ground) applied with the scope probe, there will be no useful information in that waveform other than the fact that the circuit is oscillat- ing. the x2 output is sensitive to capacitive impedance so the voltage levels and the frequency will be affected
x1227 rev 1.1.20 1/13/03 characteristics subject to change without notice. 23 of 28 www.xicor.com by the parasitic elements in the scope probe. applying a scope probe can possibly cause a faulty oscillator to start up, hiding other issues (although in the xicor rtcs, the internal circuitry assures startup when using the proper crystal and layout). the best way to analyze the rtc circuit is to power it up and read the real time clock as time advances. backup battery operation many types of batteries can be used with the xicor rtc products. 3.0v or 3.6v lithium batteries are appropriate, and sizes are available that can power a xicor rtc device for up to 10 years. another option is to use a supercapacitor for applications where vcc may disappear intermittently for short periods of time. depending on the value of supercapacitor used, backup time can last from a few days to two weeks (with >1f). a simple silicon or schottky barrier diode can be used in series with vcc to charge the superca- pacitor, which is connected to the vback pin. do not use the diode to charge a battery (especially lithium batteries!). figure 16. supercapacitor charging circuit since the battery switchover occurs at vcc=vback- 0.1v (see figure 16), the battery voltage must always be lower than the vcc voltage during normal operation or the battery will be drained. a second consideration is the trip point setting for the system reset- function, known as vtrip. vtrip is set at the factory at levels for systems with either vcc = 5v or 3.3v operation, with the following standard options: v trip = 4.63v ?3% v trip = 4.38v ?3% v trip = 2.85v ?3% v trip = 2.65v ?3% the summary of conditions for backup battery opera- tion is given in table 8: 2.7-5.5v supercapacitor v ss v cc v back table 8. battery backup operation *since vback>2.65v is higher than vtrip, the battery is powering the entire device 1. example application, vcc=5v, vback=3.0v condition vcc vback vtrip iback reset notes a. normal operation 5.00 3.00 4.38 <<1a h b. vcc on with no battery 5.00 0 4.38 0 h c. backup mode 0 1.8 1.8-3.0 4.38 <2a l timekeeping only 2. example application, vcc=3.3v,vback=3.0v condition vcc vback vtrip iback reset a. normal operation 3.30 3.00 2.65 <<1a h b. vcc on with no battery 3.30 0 2.65 0 h c. backup mode 0 1.8 1.8 3.0* 2.65 <2a* l timekeeping only d. unwanted - vcc on, vback powering 2.65 - 3.30 > vcc 2.65 up to 3ma h internal vcc=vback
x1227 rev 1.1.20 1/13/03 characteristics subject to change without notice. 24 of 28 www.xicor.com referring to figure 16, vtrip applies to the internal vcc node which powers the entire device. this means that if vcc is powered down and the battery voltage at vback is higher than the vtrip voltage, then the entire chip will be running from the battery. if vback falls to lower than vtrip, then the chip shuts down and all out- puts are disabled except for the oscillator and time- keeping circuitry. the fact that the chip can be powered from vback is not necessarily an issue since standby current for the rtc devices is <2a for this mode (called main timekeeping current in the data sheet). only when the serial interface is active is there an increase in supply current, and with vcc powered down, the serial interface will most likely be inactive. one way to prevent operation in battery backup mode above the vtrip level is to add a diode drop (silicon diode preferred) to the battery to insure it is below vtrip. this will also provide reverse leakage protection which may be needed to get safety agency approval. one mode that should always be avoided is the opera- tion of the rtc device with vback greater than both vcc and vtrip (condition 2d in table 8). this will cause the battery to drain quickly as serial bus communica- tion and non-volatile writes will require higher supplier current. performance data i back performance 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 i back vs. temperature multi-lot process variation data temperature c -40 25 60 85 i back (a) 3.3v 1.8v
x1227 rev 1.1.20 1/13/03 characteristics subject to change without notice. 25 of 28 www.xicor.com packaging information 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.019 (0.49) pin 1 pin 1 index 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4x) 7 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0 - 8 x 45 8-lead plastic, soic, package code s8 note: all dimensions in inches (in p arentheses in millimeters) 0.250" 0.050"typical 0.050" typical 0.030" typical 8 places footprint
x1227 rev 1.1.20 1/13/03 characteristics subject to change without notice. 26 of 28 www.xicor.com packaging information note: all dimensions in inches (in p arentheses in millimeters) 8-lead plastic, tssop, package code v8 see detail a .031 (.80) .041 (1.05) .169 (4.3) .177 (4.5) .252 (6.4) bsc .025 (.65) bsc .114 (2.9) .122 (3.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0 8 .010 (.25) .019 (.50) .029 (.75) gage plane seating plane detail a (20x) (4.16) (7.72) (1.78) (0.42) (0.65) all measurements are typical
x1227 rev 1.1.20 1/13/03 characteristics subject to change without notice. 27 of 28 www.xicor.com ordering information note: for appropriate volume, any v trip value from 2.6 to 4.7v may be ordered via xicor s customer speci cation program (cspec). v cc range v trip package operating temperature range part number 2.7 5.5v 4.63v 112mv 8l soic 0 70 c x1227s8-4.5a -40 85 c x1227s8i-4.5a 2.7 5.5v 4.63v 112mv 8l tssop 0 70 c x1227v8-4.5a -40 85 c x1227v8i-4.5a 2.7 5.5v 4.38v 112mv 8l soic 0 70 c x1227s8 -40 85 c x1227s8i 2.7 5.5v 4.38v 112mv 8l tssop 0 70 c x1227v8 -40 85 c x1227v8i 2.7 5.5v 2.85v 100mv 8l soic 0 70 c x1227s8-2.7a -40 85 c x1227s8i-2.7a 2.7 5.5v 2.85v 100mv 8l tssop 0 70 c x1227v8-2.7a -40 85 c x1227v8i-2.7a 2.7 5.5v 2.65v 100mv 8l soic 0 70 c x1227s8-2.7 -40 85 c x1227s8i-2.7 2.7 5.5v 2.65v 100mv 8l tssop 0 70 c x1227v8-2.7 -40 85 c x1227v8i-2.7
x1227 rev 1.1.20 1/13/03 characteristics subject to change without notice. 28 of 28 www.xicor.com limited warranty devices sold by xicor, inc. are covered by the warranty and patent indemni cation provisions appearing in its terms of sale only. xicor, inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the descr ibed devices from patent infringement. xicor, inc. makes no warranty of merchantability or tness for any purpose. xicor, inc. reserves the right to discontinue production and change speci cations and prices at any time and without notice. xicor, inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a xicor, inc. product. no o ther circuits, patents, or licenses are implied. copyrights and trademarks xicor, inc., the xicor logo, e 2 pot, xdcp, xbga, autostore, direct write cell, concurrent read-write, pass, mps, pushpot, block lock, identiprom, e 2 key, x24c16, secureflash, and serialflash are all trademarks or registered trademarks of xicor, inc. all other brand and produc t names mentioned herein are used for identification purposes only, and are trademarks or registered trademarks of their respective holders. u.s. patents xicor products are covered by one or more of the following u.s. patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084, 667; 5,153,880; 5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. foreign patents and addition al patents pending. life related policy in situations where semiconductor component failure may endanger life, system designers using this product should design the sy stem with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. xicor s products are not authorized for use in critical components in life support devices or systems. 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) sup port or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to res ult in a signi cant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. ?xicor, inc. 2003 patents pending part mark information 8-lead tssop yww xxxxx 1227al = 4.5 to 5.5v, 0 to +70 c, v trip = 4.63v 112mv 1227am = 4.5 to 5.5v, -40 to +85 c, v trip = 4.63v 112mv 1227 = 4.5 to 5.5v, 0 to +70 c, v trip = 4.38v 112mv 1227i = 4.5 to 5.5v, -40 to +85 c, v trip = 4.38v 112mv 1227an = 2.7 to 5.5v, 0 to +70 c, v trip = 2.85v 100mv 1227ap = 2.7 to 5.5v, -40 to +85 c, v trip = 2.85v 100mv 1227f = 2.7 to 5.5v, 0 to +70 c, v trip = 2.65v 100mv 1227g = 2.7 to 5.5v, -40 to +85 c, v trip = 2.65v 100mv 8-lead soic x1227 x xx blank = 8-lead soic al = 4.5 to 5.5v, 0 to +70 c, v trip = 4.63v 112mv am = 4.5 to 5.5v, -40 to +85 c, v trip = 4.63v 112mv blank = 4.5 to 5.5v, 0 to +70 c, v trip = 4.38v 112mv i = 4.5 to 5.5v, -40 to +85 c, v trip = 4.38v 112mv an = 2.7 to 5.5v, 0 to +70 c, v trip = 2.85v 100mv ap = 2.7 to 5.5v, -40 to +85 c, v trip = 2.85v 100mv f = 2.7 to 5.5v, 0 to +70 c, v trip = 2.65v 100mv g = 2.7 to 5.5v, -40 to +85 c, v trip = 2.65v 100mv

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